1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) cell structures of the type including storage cells having an access transistor and a storage trench capacitor, and the memory array designs using these cells.
2. Description of the Prior Art
U.S. Pat. No. 4,651,184 issued Mar. 17, 1987, to Malhi and entitled DRAM CELL AND ARRAY describes a DRAM cell and array of cells, together with a method of fabrication, wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bitline on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.
U.S. Pat. No. 4,673,962 issued Jun. 16, 1987, to Chatterjee et al. and entitled VERTICAL DRAM CELL AND METHOD discloses DRAM cells and arrays of cells on a semiconductor substrate, together with methods of fabrication, wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trench sidewalls with wordlines and/or bitlines crossing over the cells.
U.S. Pat. No. 4,683,486 issued Jul. 28, 1987, to Chatterjee and entitled DRAM CELL AND ARRAY discloses a DRAM cell and array of cells, together with a method of fabrication, wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel, and drain and one capacitor plate are formed in a layer of material inserted into the trench and insulated from the substrate; the gate and other capacitor plate are formed in the substrate trench sidewall. In preferred embodiments bitlines on the substrate surface connect to the inserted layer, and wordlines on the substrate surface are formed as diffusions in the substrate which also form the gate. The trenches and cells are formed in the crossings of bitlines and wordlines; the bitlines and the wordlines form perpendicular sets of parallel lines.
U.S. Pat. No. 4,649,625 issued Mar. 17, 1987, to Lu and entitled DYNAMIC MEMORY DEVICE HAVING A SINGLE-CRYSTAL TRANSISTOR ON A TRENCH CAPACITOR STRUCTURE AND A FABRICATION METHOD THEREFOR describes dynamic random access memory (DRAM) devices wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+type substrate containing heavily doped N+polysilicon. A composite film of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 is provided for the capacitor storage insulator. A thin layer of SiO.sub.2 is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO.sub.2 layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.
U.S. Pat. No. 4,688,063 issued Aug. 18, 1987 to Lu et al, and entitled DYNAMIC RAM CELL WITH MOS TRENCH CAPACITOR IN CMOS describes Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
U.S. Pat. No. 4,833,516 issued May 23, 1989 to Hwang et al entitled HIGH DENSITY MEMORY CELL STRUCTURE HAVING A VERTICAL TRENCH TRANSISTOR SELF-ALIGNED WITH A VERTICAL TRENCH CAPACITOR AND FABRICATION METHODS THEREFOR describes a high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls of the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and includes steps for growing epitaxial layers wherein an opening is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.
U.S. Pat. No. 4,728,623 issued Mar. 1, 1988 to Lu et al entitled FABRICATION METHOD FOR FORMING A SELF-ALIGNED CONTACT WINDOW AND CONNECTION IN AN EPITAXIAL LAYER AND DEVICE STRUCTURES EMPLOYING THE METHOD describes a fabrication process for providing an epitaxial layer on a silicon substrate and over predefined insulator-capped islands which forms a self-aligned contact window in the epitaxial layer.
Application of the method to a three-dimensional dynamic random access memory (DRAM) device structure is shown, with an access transistor formed in monocrystalline silicon stacked on top of a trench capacitor. A fabrication method therefor is shown wherein the contact window for the source-to-trench connection is formed by self-aligned lateral epitaxial growth, followed by a contact-connection formation step using either a second epitaxial growth or a CVD refill and strapping process. The invention can be further applied to other device structures using the described principles, and more specifically to an inverter structure having the driver device stacked over the load-resistor as another example, which can be used as a basic building circuit unit and static RAM cell.
Japanese Patent J62-040759 issued Feb. 21, 1987, and entitled SEMICONDUCTOR MEMORY describes a technique to further increase the capacity of a storage trench capacitor without increasing the size of a memory by increasing the center of a groove wider than the groove opening of a prescribed pattern.
Japanese Patent J61-285752 issued Dec. 16, 1986, and entitled SEMICONDUCTOR MEMORY DEVICE provides a structure for a memory cell optimized for a large capacity memory by providing a slant surface at the upper part of a groove, forming one transistor on the plane surface and forming one capacitor on the groove, thereby reducing the substantial plane area of the memory cell.
Japanese Patent J61-079252 issued Apr. 22, 1986, and entitled, MANUFACTURE OF SEMICONDUCTOR MEMORY DEVICE discloses a method to form a large capacitance having high withstanding voltage in a fine region for proving a DRAM having high performance by conducting the formation of a groove in a MOS capacitance region and the burying of a field insulating film through self-alignment without etching the silicon substrate.
Japanese Patent J61-145853 issued Jul. 3, 1986, and entitled SEMICONDUCTOR MEMORY DEVICE discloses a method for fabricating a trench capacitor wherein the entire face of the capacitor functions as a capacitance without reducing writing voltage. The trench capacitor is formed with an impurity-implanted region with a conductive type opposite to the semiconductor substrate.
The publication in the IBM Technical Disclosure Bulletin, Vol. 29, No. 5, October 1986, pp. 2335-2340, describes a high density vertical trench DRAM cell wherein the transfer device is oriented in the vertical direction and is positioned over the trench storage capacitor. A shallow trench filled with polysilicon or polycide serves as the MOS transfer device gate. Transfer MOSFETs of adjacent cells share the same gate.
Also see the publication in the IBM Technical Disclosure Bulletin, Vol. 27, No. 11, April 1985, pp. 6694-6697, which describes a one-transistor dynamic RAM cell requiring less surface area which is constructed by burying the cell storage capacitor beneath the drain.
The publication entitled, "Trench Capacitor Cell with Double Diffused Structure for Megabit Dynamic RAMS," by M. Yoneda, S. Satoh, H. Ozaki, M. Hirayama, M. Yamada and T. Yamazaki (Japan Soc. Appl. Phys., Tokyo, Japan; 1986 Symposium on VLSI Technology, Digest of Technical Papers, San Diego, CA., May 28-30, 1986, pp. 77-78) states that as the pattern size of LSI DRAMs gets smaller, deeper trenches and smaller isolation widths are required. However, the trench structure without p+ diffusion has a scale down limitation because of the leakage between trench capacitor cells and large collection efficiency. A trench capacitor cell is proposed with double diffused structure that has the advantage of scaling down the pattern size by decreasing the depletion layer. It is promising for the realization of megabit dynamic RAMS.
The publication entitled, "Submicron CMOS Technologies for Four Megabit Dynamic RAM," by H. Ishichi, T. Watanabe, K. Kishi, M. Ishikawa, N. Goto, T. Tanaka, T. Mochizuki and O. Ozawa (IEEE, New York, N.Y.; International Electron Devices Meeting; Technical Digest, Washington, D.C., Dec. 1-4, 1985, pp. 706-709) teaches that submicron CMOS technologies have been developed for an experimental 4-Mb dynamic RAM. The main features are a trench capacitor cell, a triple poly single metal process, and a twin tub CMOS technology. The trench capacitor cells are formed in an optimized p well in order to prevent leakage current between adjacent trench capacitors and to reduce soft error rate. The minimum gate lengths of NMOS and PMOS transistor are 0.8 mu m and 1.2 mu m, respectively. The technologies have been verified using test vehicles and a 256 Kbit dynamic RAM chip.
The publication entitled "High-Speed Sensing Scheme for CMOS DRAM's" by S. H. Dhong, N. C-C. Lu, W. Hwang and S. A. Parke (IEEE Journal of Solid State Circuits, Vol. 23, No. 1, Feb. 1988, pp. 34-40), describes a sensing scheme for CMOS DRAM's wherein a significant improvement in sensing speed over the half-VDD bitline precharge sensing scheme is obtained by precharging the bitline to approximately 2/3-VDD. The 2/3-VDD sensing with a limited bitline swing has several unique advantages over the half-VDD sensing scheme such as a faster signal development time, reduced power consumption and smaller noise. Also it is particularly suitable for high-performance high-density CMOS DRAM's, where boosting the wordlines is difficult to achieve because of device reliability concerns in the scaled down devices.
The publication "Offset Word-Line Architecture for Scaling DRAM's to the Gigabit Level" by R.E. Scheuerlein and J.D, Meindl (IEEE Journal of Solid State Circuits, Vol. 23, No. 1, Feb. 1988 pp. 41-47) describes an alternate to the boosted wordline DRAM architecture which is scalable to the gigabit level and avoids the problems of poor performance and high gate fields of conventional boosted wordline circuits is described. The alternative is called an offset wordline architecture because the cell switch is changed to depletion mode and the wordline is pulled beyond the cell switch device's source voltage rather than boosted beyond its drain voltage.